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[Other] mendianlu

Description: 本文件包是在MAX+plus II 软件环境下验证门电路的逻辑功能-This document packet was MAX+ Plus II software environment to verify the logic function circuit door
Platform: | Size: 12288 | Author: 罗理平 | Hits:

[Other] count

Description: 本文件包是在MAX+plus II 软件环境下实现计数器的逻辑功能-This document packet was MAX+ Plus II software environment counters realize the logic function
Platform: | Size: 58368 | Author: 罗理平 | Hits:

[Embeded-SCM Develop] EDA12

Description: EDA技术应用.用QUARTUES II 实现EDA技术实验操作,类似于精典的MAX+PLUS-EDA applications. QUARTUES II with EDA technology to achieve the experimental operation, similar to the classical MAX+ PLUS
Platform: | Size: 3998720 | Author: 曾伟 | Hits:

[VHDL-FPGA-Verilog] VHDLandDigitalCircuitDesign

Description: 本书系统地介绍了一种硬件描述语言，即VHDL语言设计数字逻辑电路和数字系统的新方法。这是电子电路设计方法上一次革命性的变化，也是迈向21世纪的电子工程师所必须掌握的专门知识。本书共分12章，第l章---第8章主要介绍VHDL语言的基本知识和使用VHDL语言设计简单逻辑电路的基本方法；第9章和第10章分别以定时器和接口电路设计为例，详述了用VHDL语言设计复杂电路的步骤和过程；第11章简单介绍了VHDL语言93版和87版的主要区别；第12章介绍了MAX+plus II的使用说明。 本书以数字逻辑电路设计为主线，用对比手法来说明数字逻辑电路的电原理图和VHDL语言程序之间的对应关系，并列举了众多的实例。另外，还对设计中的有关技术，如仿真、综合等作了相应说明。本书简明扼要，易读易懂。它可作为大学本科和研究生的教科书，也可以作为一般从事电子电路设计工程师的自学参考书。
Platform: | Size: 18693120 | Author: qinlei | Hits:

[VHDL-FPGA-Verilog] mimasuo_VHDL

Description: 简述了V HDL 语言的功能及其特点,并以 8 位串行数字锁设计为例,介绍了在Max + plus Ⅱ10. 2 开发软件下,利用V HDL 硬件描述语言设 计数字逻辑电路的过程和方法。并设计了密码锁
Platform: | Size: 356352 | Author: wang | Hits:

[midi program] Music

Description: MAX plus VHDL语言 实现音乐的演奏-MAX plus VHDL language music recital
Platform: | Size: 4096 | Author: gjx | Hits:

[VHDL-FPGA-Verilog] f_adder

Description: 在EDA的MAX+PLUS II开发环境下用VHDL编写的全加器-In the EDA
Platform: | Size: 56320 | Author: 林超勇 | Hits:

[VHDL-FPGA-Verilog] ADD

Description: 在MAX+PLUS II环境下用VHDL编写的加法器-In MAX+ PLUS II environment prepared using VHDL Adder
Platform: | Size: 34816 | Author: 林超勇 | Hits:

[Other] clock

Description: 本文介绍一种利用 EDA技术 和VHDL 语言 ,在MAX+PLUSⅡ环境下,设计了一种新型的智能密码锁。它体积小、功耗低、价格便宜、安全可靠,维护和升级都十分方便,具有较好的应用前景-This paper presents a use of EDA technologies and VHDL language, in MAX+ PLUS Ⅱ environment, design a new type of intelligent locks. Its small size, low power consumption, cheap, safe, reliable, maintenance and upgrade are very convenient, has good application prospects
Platform: | Size: 67584 | Author: 叶仔 | Hits:

[ELanguage] QPSK

Description: 用MAX+plusⅡ设计实现QPSK解调器。-With MAX+ Plus Ⅱ design QPSK demodulator.
Platform: | Size: 1024 | Author: li | Hits:

[Other] CPLDMAXplus

Description: CPLD数字电路设计——使用MAX+plusⅡ入门篇.rar 不能错过的书籍-CPLD digital circuit design- the use of MAX+ Plus Ⅱ entry papers. Rar can not miss books
Platform: | Size: 13341696 | Author: twinslizzy | Hits:

[Windows Develop] MAXPLUGS3

Description: 介绍max+plus的安装和简单的使用方法。-Introduction max+ Plus installation and simple to use.
Platform: | Size: 267264 | Author: libing | Hits:

[MPI] exercise1

Description: 在软件MAX+plus II环境中，设计了一台RISC模型机，具有以下功能：输入包含10个整数（无符号数）的数组M，按从小到大的顺序输出这10个数。-In terms of software MAX+ Plus II environment, the design model of a RISC machine, has the following features: input contains 10 integer (unsigned number) of the array M, according to the order from small to large number of the output of these 10.
Platform: | Size: 937984 | Author: 陈自分 | Hits:

[VHDL-FPGA-Verilog] FPGAforDLC

Description: 采用Altera公司的FPGA芯片，在MAX+plus II软件平台上实现多路HDLC电路-Using Altera s FPGA chips, in MAX+ Plus II software platform to achieve multi-channel HDLC circuit
Platform: | Size: 62464 | Author: yangj2 | Hits:

[VHDL-FPGA-Verilog] MAXPLUS

Description: MAX+PLUSⅡ的学习应用教程,适用于基本的VHDL开发-MAX+ PLUS Ⅱ Application Tutorial learning for the development of the basic VHDL
Platform: | Size: 13424640 | Author: wanghui | Hits:

[VHDL-FPGA-Verilog] MyProject

Description: 3-8译码器的仿真实验。本实验选用的仿真开发软件是MAX+plus II Version 9.3，原理图源文件保存在MyProject目录中，为138decoder.gdf，另有我写的实验报告，呵呵，适合仿真入门-3-8 decoder simulation. Selected in this experiment simulation software is MAX+ Plus II Version 9.3, schematic source files stored in the MyProject directory for 138decoder.gdf, otherwise I write experimental reports, Ha ha, suitable for simulation of induction
Platform: | Size: 224256 | Author: zhang | Hits:

[VHDL-FPGA-Verilog] bid_shift_reg

Description: VHDL语言编写，实现双向移位寄存器功能，在MAX+plus软件下实现-VHDL language to achieve bi-directional shift register function MAX+ Plus software to achieve
Platform: | Size: 2079744 | Author: 画眉 | Hits:

[VHDL-FPGA-Verilog] decoder_2_10

Description: 采用VHDL语言编写的二-十进制编码器，在MAX+plus软件上实现，其中包括演示截图。-Using VHDL languages II- Decimal encoder, in MAX+ Plus software to achieve, including the demo screenshot.
Platform: | Size: 1793024 | Author: 画眉 | Hits:

[VHDL-FPGA-Verilog] decoder_3_8

Description: 采用VHDL语言编写8线-3线优先编码器，在MAX+plus软件下实现。-Using VHDL language-3 line 8 line priority encoder, in MAX+ Plus software to achieve.
Platform: | Size: 2520064 | Author: 画眉 | Hits:

[VHDL-FPGA-Verilog] 61EDA_D702

Description: 4位电子智能密码锁，基于VHDL语言设计，MAX+PLUSⅡ环境下实现-4 electronic smart locks, based on the VHDL design language, MAX+ PLUS Ⅱ environment to achieve
Platform: | Size: 1101824 | Author: spy0501 | Hits:
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